The present invention relates to a CMOS integrated circuit technology.
A recognized difficulty with both short-channel and high-voltage MOS technologies is impact ionization at the drain/channel boundary, since the high peak electric fields normally encountered in this location lead to injection of hot carriers into the gate oxide (producing a shift in he device threshold according to the devices operating history), and to reduced avalanche breakdown voltage, and to increased parasitic substrate current. The electric filed generated by the gate exacerbates the problem of avalanche breakdown into the drain boundary, and this is particularly severe if the drain boundary is very close to the gate corner, where the gate field is normally at a maximum. All these effects are particularly, difficult in the N-channel devices in CMOS technology, both at small geometries (e.g. 1 micron channel length at 5 volts) and at high voltages (4 microns channel length at 20 volts).
In digital CMOS circuits parasitic substrate currents caused by impact ionization flow during the switching transients when both N and P-channel devices are turned on. This can give rise to `substrate bounce` which could cause latch-up, debiasing or the discharge of floating nodes. (These are more good reasons for using epi on a P+ substrate). In analog circuits the situation is potentially more serious since N-channel source follower type configurations could be biased such that a significant parasitic substrate current flows continuously. Perhaps the most serious effect of all is hot carrier injection into the gate oxide which can cause long term threshold shifts and transconductance degradation. Of course, all these problems become more severe as the gate oxide is scaled while the supply voltage is kept constant.
Since the coefficient of impart ionization is approximately an order of magnitude higher for electrons that for holes, the N-channel device is the limitation to realizing short channel devices for high voltage applications. The present invention teaches CMOS techniques for making the N-channel device in a CMOS process `hot-carrier resistant`. These techniques introduce lightly doped N regions between the channel and the N+ source/drain regions. This structure spreads the high electric filed at the drain pinch-off region into the N- extension, thereby increasing the drain breakdown voltage, reducing impact ionization, and consequently reducing hot-electron emission. These advantages are realized at the cost of a low dose phosphorus blanket implant, no extra masking steps are required.
Significant attention has been paid to problems of this nature in the prior art of NMOS devices. For example, U.S. Pat. No. 4,356,040, which is hereby incorporated by reference, teaches the use of gate sidewall oxide to reduce the gate/drain overlap, or to provide for gate/drain underlap. Ogura et al, "Design and Characteristics of the Lightly Doped Drain/Source (LDD) Insulated Gate Field-Effect Transistor," IEEE Journal of Solid State Circuits, Volume SC-15, Pages 424 and following (1980) together with references cited therein, all of which are hereby incorporated by reference, discloses the structure of lightly doped drain regions and discusses their advantages. Other art is believed to expressly teach the formation of a lightly doped drain region which is formed by a reachthrough source/drain implant which is partially screened by a sidewall oxide.
The incorporation of a lightly doped drain structure in a CMOS process presents several peculiar problems, and it is these specific problems which the present invention addresses.
In particular, it is an object of the present invention to provide a method for forming lightly doped drain extension regions (LDD regions) in a CMOS technology.
It is a further object of the present invention to provide a method for fabricating LDD regions in a CMOS technology, without requiring any additional masking steps.
A particular difficulty in CMOS technology, as discussed above, is that only the N-channel devices need the LDD region at the drain boundary, since the impact ionization coefficient for holes is far lower than for electrons, as discussed above.
Thus, it is an object of the present invention to provide a method for fabricating CMOS devices in which the N-channel devices incorporate LDD regions, whereas the P-channel devices do not.
It is a further object of the present invention to provide a method for fabricating CMOS devices wherein the N-channel devices but not the P-channel devices incorporate lightly doped drain regions, without requiring any additional masking steps.
A further problem with the use of lightly doped drain regions is that they degrade device characteristics in several ways. In particular, the series resistance of the device can be increased substantially, and the transconductance of the device will also be lower. Both of these effects are sensitive to the length of the LDD regions. That is, it is desirable that the LDD extension regions not be much longer than is necessary, considering the operating voltage of the device. In particular, if the LDD regions are not self-aligned to the gate and source/drain regions, then the LDD regions must be at least two alignment tolerances wide, since otherwise normal alignment variation could produce some devices which had no LDD region at all. These devices would be inoperative and degrade yield. Thus, it is highly desirable that the lightly doped drain extension regions be self-aligned to the gate and also to the source/drain regions.
It is a further object of the present invention to provide a CMOS processing technology wherein lightly doped drain extension regions are self-aligned to both the gate and to the source/drain regions.
It is a further of the present invention to provide a CMOS technology wherein lightly doped drain extension regions are self-aligned both to gate regions and to source/drain regions in N-channel devices only and do not occur in P-channel devices, without requiring any additional masking steps.
The above problems are particularly acute with high voltage devices. High voltage CMOS devices are highly attractive for many applications, including consumer devices, control devices, and devices for environments where electrical noise is very high. However, it is quite difficult to get the geometries of a high voltage CMOS process down to geometry suitable for LSI density. In addition, the mask counts for the high-voltage CMOS process must be very carefully controlled, since even a technologically possible chip is useless unless the cost per chip as-fabricated times the yield produces an acceptably low net cost figure. That is, a crucial parameter in high voltage CMOS applications is the combination of low mask count and small geometries.
Thus, it is an object of the present invention to provide a high voltage CMOS process having very low mask count and relatively small geometries.
The length of the LDD region can be particularly critical in a high voltage CMOS process. This is because, in a very high voltage process, a low dopant concentration will be typically used in the LDD region to achieve the necessary gradual doping profile at the channel/LDD boundary, but such low dopant concentrations necessarily imply a very high resistively within the LDD region itself, and therefore the series resistance of the device will be drastically degraded as the length of the LDD region is increase. On the other hand, it is necessary that the LDD region in a very high voltage device not be too short, since the desired gradual dopant profile may thereby be truncated. That is, use of non-self-aligned LDD regions may be optimal in a high voltage process because the substantial total width of the source and drain side LSS's impose a total additional series resistance in the device which is significantly larger than that required if the LDD width on both sides were merely minimal.
According to the present invention there is provided:
A method for fabrication of a CMOS device, comprising the steps of:
providing a semiconductor substrate;
defining moat regions at the surface of said substrate;
introducing N-type impurities into selected portions of said substrate to form a plurality of N-tank regions;
forming an insulated conductive gate layer over portions of said substrate to define a predetermined plurality of device locations within said moat regions, said device locations comprising both N-channel locations regions and P-channel device locations;
(a) introducing a light dose of an N-type dopant into a shallow depth of said substrate surface overall, both in desired locations of lightly doped drain extension regions and in other locations;
depositing a conformal oxide overall;
(b) providing a patterned mask layer to cover the locations of said N-channel devices, removing said conformal oxide where not covered by said masking layer, introducing a heavy dose of P-type impurities to form P-type source/drain regions in predetermined locations where the surface of said substrate is exposed, and removing said first masking layer;
(c) depositing a patterned masking layer to cover a plurality of said P-channel device locations, anisotropically etching said conformal oxide over said N-type device regions to leave sidewall oxides at the sidewalls of said gates over said N-type device regions, and implanting a high dose of an N-type impurity to form N-type sources and drains, whereby said N-channel devices comprise a lightly doped drain extension region separating said respective source/drain regions thereof from said respective channel regions thereof; and
connecting said respective source/drain and gates to provide a desired circuit function;
wherein all of step (a) is performed before step (6), and all of step (6) is performed before step (c).